Charge trapping memory device with two separated non-conductive charge trapping inserts and method for making the same

ABSTRACT

A charge trapping memory device with two separated non-conductive charge trapping inserts is disclosed. The charge trapping memory device has a silicon substrate with two junctions. A gate oxide (GOX) is formed on top of the silicon substrate and between the two junctions. A polysilicon gate is defined over the GOX. A layer of bottom oxide (BOX) is grown on top of the silicon substrate and a conformal layer of top oxide (TOX) is grown along the bottom and the sidewalls of the polysilicon gate. Two charge trapping inserts are located beside the GOX and between the BOX and the TOX. The polysilicon gate needs to be at least partially over each of the two charge trapping inserts. The charge trapping inserts are made from a non-conductive charge trapping material. A method for fabricating such a device is also described.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to a semiconductor memorydevice, and more particularly, to a charge trapping memory device withtwo separated non-conductive charge trapping inserts and a method formaking such a device.

2. Description of the Related Art

As is well known in the art, a nitride read only memory (NROM) deviceuses an oxide-nitride-oxide (ONO) structure as the gate insulator aswell as the charge trapping layer. A NROM device is programmed byinjecting electrons into the nitride layer of the ONO structure via thechannel hot electron (CHE) injection method. The trapped electrons inthe nitride layer of the ONO structure can be erased by injecting holesinto the place where the electrons are stored via the band-to-band hot(BTBH) hole injection method.

Although a NROM device is widely used in the semiconductor industry, ithas the following drawbacks. First of all, a NROM device has ahard-to-erase problem after cycling. During the erasing process of anNORM device via the BTBH hole injection method, it is difficult toinject the holes to exactly where the electrons are trapped, and it ishard to match exactly the number of the trapped electrons with thenumber of injected holes, which leads to the phenomenon of thehard-to-erase problem. Next, an NROM device has wide threshold voltageV_(T) distribution. In fabricating an NROM device, the plasma chargingor UV-charging process can cause the initial V_(T) to shift and broaden.If some of the injected electrons are shifted towards the center of thenitride layer of the ONO structure that is far away from the place wherethe electrons are injected, the initial wide V_(T) distribution isfurther out of control. The wide V_(T) distribution cannot be reset backto a lower state. Furthermore, an NROM device could have severe secondbit effect. Because an NROM device is capable of 2-bit operation bystoring two charges towards the ends of the nitride layer of the ONOstructure, as the charges at both ends of the nitride layer of the ONOstructure gets larger, the charges of both bits will interact with eachother during a reverse read operation, which leads to the undesirablesecond bit effect. Finally, an NROM device has a hard-to-shrink problemdue to the fact that its doping profile mainly controls the electronprofile. Thus, the local charge profile will overlap with the otherlocal charge profile, which makes an NROM device difficult to shrink.

Another prior art floating gate memory device utilizes two separatedpolysilicon inserts in the gate insulator next to the junctions. Thisfloating gate memory device will have reliability problems such asstress-induced leakage current (SILC) and erratic bits.

In view of the foregoing, there is a need for a new charge trappingmemory device and its fabrication method that will overcome theabove-mentioned drawbacks of the NROM device and a floating gate memorydevice.

SUMMARY OF THE INVENTION

Broadly speaking, the present invention fills this need by providing anew charge trapping memory device with two separated non-conductivecharge trapping inserts which are surrounded by oxide layers. A methodfor fabricating this new device is also described.

In accordance with one aspect of the present invention, a new chargetrapping memory device is provided. This charge trapping memory deviceincludes a silicon substrate with two junctions. A gate oxide (GOX) isformed on top of the silicon substrate and between the two junctions,and a polysilicon gate is defined over the GOX. A layer of bottom oxide(BOX) is grown on top of the silicon substrate, while a conformal layerof top oxide (TOX) is grown along the bottom and sidewalls of thepolysilicon gate. Two charge trapping inserts are located beside the GOXand between the BOX and the TOX. The polysilicon gate is at leastpartially over each of the two charge trapping inserts. In oneembodiment, two high density plasma oxide blocks are formed on top ofthe BOX and next to the two charge trapping inserts and the TOX. A layerof n-plus doped polysilicon is defined over the polysilicon gate and thetwo high density plasma oxide blocks.

In accordance with another aspect of the present invention, a method forfabricating such a new charge trapping memory device is also described.In this method, a silicon substrate having a layer of GOX formed thereonis provided. A polysilicon gate is defined over the GOX. Two undercutregions are formed at sidewalls of the GOX along the width of the GOX.In one embodiment, the two undercut regions are formed by thehydrofluoric acid during a self-limited etching process. An oxidationprocess causes a layer of BOX grown on top of the silicon substrate anda conformal layer of TOX grown along the bottom and sidewalls of thepolysilicon gate. The BOX and the TOX are grown simultaneously. Twocharge trapping inserts are formed by depositing a non-conductive chargetrapping material into the two undercut regions. In one embodiment, asilicon nitride block is defined over the polysilicon gate to protectthe polysilicon gate during the fabrication process. The silicon nitrideblock needs to be lifted off after the two charge trapping inserts areformed. In another embodiment, two high density plasma oxide blocks areformed on top of the BOX and next to the two charge trapping inserts andthe TOX. Then, a layer of n-plus doped polysilicon is deposited over thepolysilicon gate and the two high density plasma oxide blocks. Anotherlayer of tungsten silicide is defined over the layer of n-plus dopedpolysilicon to reduce the resistance among the memory devices for amemory array structure.

This new charge trapping memory device avoids the drawbacks of a NROMdevice and a floating gate memory device mentioned previously. This newdevice has no erratic bit and no stress-induced leakage current becauseof the non-conductive property of the charge trapping material. It canprecisely control the length of the charge trapping layer by controllingthe length of the charge trapping inserts, which should be shorter thanthe length of the channel hot electron (CHE) injection or theband-to-band hot (BTBH) hole injection. The best location for the chargetrapping inserts is where the CHE and the BTBH injection takeplace. As aresult, it is easy to erase the charges trapped in this new devicebecause the locations of the charges are known and the lengths of thecharge trapping inserts are limited. Since the two charge trappinginserts are separated by the GOX that is a non-charge trapping material,the wide threshold voltage V_(T) distribution problems and the initialV_(T) shift problem can be corrected. Furthermore, because the chargedregions are limited by the lengths of the charge trapping inserts ratherby the injection ranges, which causes a narrower charge trapping regionnext to a junction, a relatively smaller read voltage is enough toovercome the second bit effect. In addition, since the charge profilesof this new charge trapping memory device are limited to the lengths ofthe charge trapping inserts, the two charge profiles will not overlapwith each other. Thus, it is possible to shrink the charge trappingmemory device.

The charge trapping inserts has a non-conductive charge trappingmaterial property. The non-conductive charge trapping material can beany material that is capable of trapping a certain amount of charge solong as it is non-conductive. In one example, the non-conductive chargetrapping material can be silicon nitride, aluminum oxide, hafnium oxide,etc. Of course, the exemplary non-conductive charge trapping materialsare not intended to be exhaustive nor limit the invention to the precisematerials provided for example purposes.

It is to be understood that the foregoing general description and thefollowing detailed description are exemplary and explanatory only andare not restrictive of the invention, as claimed.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are incorporated in and constitute partof this specification, illustrate exemplary embodiments of the inventionand together with the description serve to explain the principles of theinvention.

FIG. 1 illustrates a cross-sectional view of a charge trapping memorydevice in accordance with one embodiment of the present invention.

FIG. 2A-2I illustrate an exemplary method for fabricating the chargetapping memory device shown in FIG. 1.

FIG. 3 is a top view of a charge trapping memory array structure withnine charge trapping memory devices fabricated by using the methodillustrated in FIG. 2A-2I.

FIG. 3A is a cross-sectional view of the charge trapping memory arraystructure viewed from the A-A′ line.

FIG. 3B is a cross-sectional view of the charge trapping memory arraystructure viewed from the B-B′ line.

DETAILED DESCRIPTION OF THE EXEMPLARY EMBODIMENTS

Reference is made in detail to embodiments of the invention. While theinvention is described in conjunction with the embodiments, theinvention is not intended to be limited by these embodiments. On thecontrary, the invention is intended to cover alternatives, modificationsand equivalents, which may be included within the spirit and scope ofthe invention as defined by the appended claims. Furthermore, in thefollowing detailed description of the invention, numerous specificdetails are set forth in order to provide a thorough understanding ofthe invention. However, as is obvious to one ordinarily skilled in theart, the invention may be practiced without these specific details. Inother instances, well-known methods, procedures, components, andcircuits have not been described in detail so that aspects of theinvention will not be obscured.

FIG. 1 is a cross-sectional view of a charge trapping memory device 100in accordance with one embodiment of the present invention. As shown inFIG. 1, silicon substrate 110 has two doped junctions 120 a and 120 b. Agate oxide (GOX) 160 is formed on top of the silicon substrate 110 andbetween the two doped junctions 120 a and 120 b. A polysilicon gate 170is defined over the GOX. A layer of bottom oxide 130 (BOX) is grown ontop of the silicon substrate 110, while a conformal layer of top oxide(TOX) 140 is grown along the bottom and sidewalls of the polysilicongate 170. Two charge trapping inserts 150 are located beside the GOX 160and between the BOX 130 and the TOX 140. Two high density plasma oxideblocks 180 are formed on top of the BOX 130 and next to the two chargetrapping inserts 150 and the TOX 140. A layer of n-plus dopedpolysilicon 190 is defined over the polysilicon gate 170 and the twohigh density plasma oxide blocks 180.

FIG. 2A-2I illustrate an exemplary method for fabricating the chargetrapping memory device 100 shown in FIG. 1. With reference to FIG. 2A, asilicon substrate 110 has a gate oxide (GOX) 160 formed thereon. Apolysilicon gate 170 is formed on top of the GOX 160, while a siliconnitride block 270 is formed on top of the polysilicon gate 170. Thesilicon nitride block 270 is used to protect the polysilicon gate 170during the fabricating process.

Next, as shown in FIG. 2B, two undercut regions 250 are defined by thesidewalls of the GOX 160, the bottom of the polysilicon gate 170, andthe top of the substrate 110. The two undercut regions 250 extend awidth along the width of the GOX 160. By way of example, hydrofluoricacid can be used to selectively and self-limitedly etch the sidewalls ofthe GOX 160 to create the two undercut regions 250 for a non-conductivecharge trapping material deposition therein.

Turning to FIG. 2C, an oxidation process causes a layer of BOX 130 togrow on top of the substrate 110 and to define a conformal layer of TOX140 along the bottom of the polysilicon gate 140 and the sidewalls ofthe polysilicon gate 140, and/or the silicon nitride block 270. In thisembodiment, the BOX 130 and the TOX 140 are grown simultaneously. Asshown, the oxidation process also causes the structure deformation ontop of the substrate 110 and along the bottom and sidewalls of thepolysilicon gate 170. The gaps of the undercut regions 250 becomesmaller due to the growth of the BOX 130 and the TOX 140.

Referring now to FIG. 2D, a conformal layer of a non-conductive chargetrapping material 210 is substantially deposited over the siliconnitride block 270 and extends to the substrate 110. The conformal layerof a non-conductive charge trapping material 210 fills the undercutregion 250 completely. The non-conductive charge trapping material canbe any material that is capable of trapping certain amount of charges solong as it is non-conductive. By way of an example, the non-conductivecharge trapping material can be selected from silicon nitride, aluminumoxide, hafnium oxide, etc. Of course, the listed exemplary materials arenot intended to be exhaustive or to limit the invention to the precisematerials disclosed. In one embodiment, the deposition of thenon-conductive charge trapping material can be performed by alow-pressure chemical vapor deposition (LPCVD) method. In anotherembodiment, the deposition of the non-conductive charge trappingmaterial can be carried out by a liquid phase deposition (LPD) method.

Referring next to FIG. 2E, the conformal layer of a non-conductivecharge trapping material 210, nitride for example, is oxidized for aperiod of time until the outer portion of the conformal layer of anon-conductive charge trapping material 210 which encapsulates thesilicon nitride 270 and extends to the substrate 110 is converted intoan oxidized layer 210′. The conversion happens for the entire material210, except for an inner portion of the conformal layer of anon-conductive charge trapping material 210 embedded at the undercutregions 250. As shown, the un-oxidized non-conductive charge trappingmaterial embedded at the undercut regions 250 forms two charge trappinginserts 150. In alternative embodiment for nitride, aluminum oxide, andhafnium oxide, the outer portion of the conformal layer of anon-conductive charge trapping material 210 can be removed by awet-etching process. In another embodiment, a thermal treatment isperformed at the interface between each of the charge trapping inserts150 and its surrounding oxide layers to enhance the charge trappingability of the charge trapping inserts 150.

Continuing to FIG. 2F, two junctions 120 a and 120 b are implanted nextto the two charge trapping inserts 150 on the silicon substrate 110 asshown.

With reference to FIG. 2G, a high density plasma (HDP) oxidation processis performed to fill in the spaces beside the polysilicon gate 170 andthe silicon nitride block 270. As a result, two high density plasmaoxide blocks 180 are formed as shown. Preferably, the high densityplasma oxide blocks 180 should be at least as high as the top of thesilicon nitride block 270. As is common in HDP processes, after thespaces are filled, a high density plasma oxide 280 is shown in the formof a triangle over the higher feature profiles.

As shown in FIG. 2H, the top portions of the two high density plasmaoxide blocks 180 and the excessive high density plasma oxide 280 areetched off by the hydrofluoric acid dipping process. Then, the siliconnitride block 270 is lifted off by the phosphoric acid etch. Thehydrofluoric acid dipping process also removes the top portion of theoxidized layer 210′. Because the oxidized layer 210′ and the highdensity plasma oxide blocks 180 are very similar oxide materials, forthe simplicity of the illustration, the remaining oxidized layer 210′and the remaining high density plasma oxide blocks 180 are combinedtogether and shown as the high density plasma oxide blocks 180 only.

Referring to FIG. 21, a layer of n-plus doped polysilicon 190 isdeposited over the polysilicon gate 170 and the two high density plasmaoxide blocks 180. Another layer of tungsten silicide 290 is defined overthe layer of n-plus doped polysilicon 190 to reduce the line resistancebetween the memory devices. The layer of n-plus doped polysilicon 190and the layer of tungsten silicide 290 extend along the width and thelength of the charge trapping memory device.

FIG. 3 is a top view of a charge trapping memory array structure 300with nine charge trapping memory devices fabricated by using the methodillustrated in FIG. 2A-2I. The photolithographic patterning and theetching are performed to selectively etch away portions of the layer ofn-plus doped polysilicon 190, the layer of tungsten silicide 290, andthe polysilicon gate 170 to form multiple charge trapping memorydevices. The un-etched portions of the charge trapping memory arraystructure 300 forms three lateral stripes, which are the word lines (WL)310. The vertical stripes are bit lines (BL) 320 for this chargetrapping memory array structure 300. As a result, nine charge trappingmemory devices are formed at the intersections of the three bit linesand the three word lines.

FIG. 3A is a cross-sectional view of the charge trapping memory arraystructure 300 viewed from the A-A′ line, which is actually across-sectional view of one of the nine charge trapping memory devices.As shown, silicon substrate 110 has two doped junctions 120 a and 120 b.A GOX 160 is formed on top of the silicon substrate 110 and between thetwo doped junctions 120 a and 120 b. A polysilicon gate 170 is definedover the GOX. A layer of BOX 130 is grown on top of the siliconsubstrate 110, while a conformal layer of TOX 140 is grown along thebottom and sidewalls of the polysilicon gate 170. Two charge trappinginserts 150 are located beside the GOX 160 and between the BOX 130 andthe TOX 140. Two high density plasma oxide blocks 180 are formed on topof the BOX 130 and next to the two charge trapping inserts 150 and theTOX 140. A layer of n-plus doped polysilicon 190 is defined over thepolysilicon gate 170 and the two high density plasma oxide blocks 180. Alayer of tungsten silicide 290 is defined over the layer of n-plus dopedpolysilicon 190.

FIG. 3B is a cross-sectional view of the charge tapping memory arraystructure viewed from the B-B′ line. In comparison with the FIG. 3A, theetching process etched away the layer of tungsten silicide 290, thelayer of n-plus doped polysilicon 190, and the polysilicon gate 170 atthis cross section marked by the B-B′ line.

As illustrated, the charge trapping memory device 100 contains twoseparated non-conductive charge trapping inserts that are surrounded byoxide layers. Electrons and holes can be injected into the chargetrapping inserts to alter the threshold voltage V_(T) Of the chargetrapping memory device 100. The depth of the undercut regions 250 willdefine the lengths of the charge trapping inserts 150. The gap betweenthe TOX 140 and the BOX 130 determines the thickness of the chargetrapping inserts 150. In order to provide a precise control of theinjected charges during programming, the lengths of the charge trappinginserts 150 need to be equal or shorter than the length of the channelhot electron (CHE) injection or the band-to-band hot (BTBH) injection.The best location for the charge trapping inserts 150 is where the CHEor the BTBH injection takes place. After the two charge trapping inserts150 are charged, the reading of the two bits needs to use the reverseread scheme.

The charge trapping memory device 100 overcomes the problems of a NROMdevice and a floating gate memory device mentioned previously. Due tothe non-conductive property of the charge trapping material used for thecharge trapping inserts 150, no stress-induced leakage current exists inthe charge trapping memory device 100. Unlike a floating gate memorydevice, the charge trapping memory device 100 is immune to erratic bitbecause the charge trapping memory device 100 uses two individual chargetrapping inserts 150 to store charges. Since the two charge trappinginserts 150 are separated by the GOX 160 that is not capable of trappingany charges, the threshold voltage V_(T) distribution can be preciselycontrolled. Consequently, V_(T) shift caused by the Plasma charging orUV charging can be reset by charge injection. Furthermore, because thecharged regions are limited by the lengths of the charge trappinginserts 150 rather by the injection ranges created by the CHE or theBTBH injection, which creates a narrower charge trapping region next toa junction, a relatively smaller read voltage is enough to screen outthe second bit effect. As a result, the second bit effect is minor inthis new charge trapping memory device 100. Finally, since the chargeprofiles are limited to the lengths of the charge trapping inserts 150,the two local charge profiles will not overlap with each other, whichmake the shrinkage of the charge trapping memory device 100 possible.

The foregoing descriptions of specific embodiments of the invention havebeen presented for purposes of illustration and description. They arenot intended to be exhaustive or to limit the invention to the preciseforms disclosed. Obviously, many modifications and variations arepossible in light of the above teaching. The embodiments were chosen anddescribed in order to explain the principles and the application of theinvention, thereby enabling others skilled in the art to utilize theinvention in its various embodiments and modifications according to theparticular purpose contemplated. The scope of the invention is intendedto be defined by the claims appended hereto and their equivalents.

1. A memory device, comprising: a semiconductor substrate; an insulatorlayer having an oxide property; first and second inserts defined by anon-conductive charge trapping material, the first and second insertsbeing positioned adjacent a first side and a second side of theinsulator layer; and a polysilicon gate defined over the insulator layerand at least partially over each of the first and second inserts.
 2. Thememory device as recited in claim 1, further comprising: first andsecond oxide blocks positioned respectively beside the first and secondinserts, and defined over the substrate and next to side walls of thepolysilicon gate.
 3. The memory device as recited in claim 2, furthercomprising: a polysilicon layer defined over the polysilicon gate andthe first and second oxide blocks.
 4. The memory device as recited inclaim 3, wherein the polysilicon layer is an impurity doped polysiliconlayer.
 5. The memory device as recited in claim 2, wherein the first andsecond oxide blocks are high-density plasma oxide blocks.
 6. The memorydevice as recited in claim 1, wherein the non-conductive charge trappingmaterial is selected from the group consisting of silicon nitride,aluminum oxide and hafnium oxide.
 7. The memory device as recited inclaim 1, wherein each of the first and second inserts is surrounded byoxide.
 8. A method for making a memory device, comprising: providing asemiconductor substrate; forming an insulator layer on top of thesubstrate, the insulator layer having an oxide property; formingundercut regions on a first side and a second side of the insulatorlayer; forming first and second inserts in each of the undercut regions,the first and second inserts having a non-conductive charge trappingmaterial property; forming a gate over the insulator layer, the gatebeing formed at least partially over each of the first and secondinserts.
 9. The method for making a memory device as recited in claim 8,further comprising: implanting junctions next to the first and secondinserts.
 10. The method for making a memory device as recited in claim8, further comprising: growing a top oxide layer along bottom andsidewalls of the gate, and a bottom oxide layer along the top of thesubstrate after the forming undercut regions.
 11. The method for makinga memory device as recited in claim 10, further comprising: performingthermal treatment along top interfaces between each of the first andsecond inserts and the top oxide layer and along bottom interfacesbetween each of the first and second inserts and the bottom oxide layer.12. The method for making a memory device as recited in claim 8, furthercomprising: forming high density plasma oxide blocks over the top of thesubstrate, next to sidewalls of the gate, and beside the first andsecond inserts.
 13. The method for making a memory device as recited inclaim 12, further comprising: depositing a layer of polysilicon over thehigh density plasma oxide blocks and the gate; and depositing a layer oftungsten silicide over the layer of polysilicon.
 14. The method formaking a memory device as recited in claim 13, wherein the layer ofpolysilicon is a layer of impurity doped polysilicon.
 15. The method formaking a memory device as recited in claim 12, further comprising:removing top portions of the high density plasma oxide blocks with achemical material.
 16. The method for making a memory device as recitedin claim 15, wherein the chemical material is hydrofluoric acid.
 17. Themethod for making a memory device as recited in claim 8, furthercomprising: forming a silicon nitride block over the polysilicon gate.18. The method for making a memory device as recited in claim 17,further comprising: lifting off the silicon nitride block with achemical material after the first and second inserts are formed.
 19. Themethod for making a memory device as recited in claim 18, wherein thechemical material is hot phosphoric acid.
 20. The method for making amemory device as recited in claim 8, wherein forming of undercut regionsis performed by a chemical material.
 21. The method for making a memorydevice as recited in claim 20, wherein the chemical material ishydrofluoric acid.
 22. The method for making a memory device as recitedin claim 8, wherein forming the first and second inserts is carried outby depositing a conformal layer of the non-conductive charge trappingmaterial over the gate and extending to the substrate such that theundercut regions are filled, the conformal layer of the non-conductivecharge trapping material encapsulating the gate and the insulator layer;and oxidizing an outer portion of the conformal layer of thenon-conductive charge trapping material to create the first and secondinserts;
 23. The method for making a memory device as recited in claim22, wherein depositing the conformal layer of the non-conductive chargetrapping material is performed by one of a low pressure chemical vapordeposition method and a liquid phase deposition method.
 24. The methodfor making a memory device as recited in claim 8, wherein thenon-conductive charge trapping material is selected from the groupconsisting of nitride, aluminum oxide and hafnium oxide.
 25. The methodfor making a memory device as recited in claim 8, wherein the gate is apolysilicon gate.
 26. The method for making a memory device as recitedin claim 8, further comprising: performing thermal treatment along sideinterfaces between each of the first and second inserts and theinsulator layer.
 27. The method for making a memory device as recited inclaim 8, wherein lateral length of each of the first and second insertsis equal or shorter than length of a channel hot electron injection or aband-to-band hot hole injection.
 28. The method for making a memorydevice as recited in claim 8, wherein the first and second inserts isbest placed at where a Channel Hot Electron injection or a Band-to-BandHot hole injection takes place.
 29. The method for making a memorydevice as recited in claim 8, wherein forming the first and secondinserts is carried out by depositing a conformal layer of thenon-conductive charge trapping material over the gate and extending tothe substrate such that the undercut regions are filled, the conformallayer of the non-conductive charge trapping material encapsulating thegate and the insulator layer; and etching the outer portion of theconformal layer of the non-conductive charge trapping material to createthe first and second inserts.
 30. The method for making a memory deviceas recited in claim 29, wherein depositing the conformal layer of thenon-conductive charge trapping material is performed by one of a lowpressure chemical vapor deposition method and a liquid phase depositionmethod.